Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
Conventionally, FPGAs were loaded into an Automated Test Equipment (“ATE”) multi-site testing platform for testing, with dedicated function pins being used solely for dedicated function testing. Although the example of testing FPGAs is used herein, it should be appreciated that any of a variety of known PLDs having dedicated function pins may be used. Furthermore, for purposes of clarity and not limitation, “FPGA fabric,” which may for example include programmable logic or programmable routing (“programmable logic”), is used to describe the type of testing being done for FPGAs.
An example of dedicated function pins is JTAG pins. JTAG pins conventionally have been exclusively used for dedicated function testing, such as for boundary scan (“BSCAN”) testing of ICs including FPGAs. However, having to allocate separate sets of pins for dedicated function pins as part of an ATE multi-site testing platform places an additional burden on pin constraints of such ATE multi-site testing platform. These dedicated function pins may thus effectively limit the total number of test sites available for coupling FPGAs to a single ATE multi-site testing platform for simultaneous testing of FPGAs. Accordingly, such burden may constrain test throughput. Other examples of dedicated function pins are those pins heretofore used solely for configuration of FPGA fabric for testing, but not used to access FPGA fabric for testing via application of a test pattern for example.
Non-dedicated function pins, such as input/output pins (“I/Os”), may be used for testing FPGA fabric. Some of these non-dedicated function pins are not used for testing FPGA fabric, and these non-dedicated function pins of such an FPGA may be shorted together, as is known. This shorting of some non-dedicated function pins facilitates simultaneous testing of multiple FPGAs on a single ATE multi-site testing platform. This shorting may be done with use of a circuit board, such as a “daughter card” test board, associated with an ATE multi-site testing platform integrated circuit handler (“handler”). An example of a multi-site testing platform for probe or package level semiconductor testing is the Flex test platform from Teradyne of Boston, Mass., although there other known multi-site testing platforms which may be used. However, the ability to test multiple FPGAs at the same time using a single ATE multi-site testing platform is still limited by the number of non-dedicated function pins available to receive test pattern signaling and provide such test pattern signaling to FPGA fabric.
Accordingly, it would be desirable and useful to provide means to increase test throughput for an ATE multi-site testing platform.